1. Field of the Invention
The present invention relates to power converters or power supplies, and more specifically to pulse width modulation (PWM) and pulse frequency modulation (PFM) controllers for driving a switching transistor in switching power converters.
2. Description of the Related Arts
Typical power converters include a power stage for delivering electrical power from a power source to a load, a switching device in the power stage that electrically couples or decouples the load to the power source, and a switch controller coupled to the switch for controlling the on-times and off-times of the switch. The switch is typically a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a BJT (Bipolar Junction Transistor). A switch controller includes a pulse generator which generates a pulse for driving the switch. The positive and negative parts of the pulse correspond to the on-times and off-times of the switch. The on-times and off-times of the switch can be modified by the switch controller based upon a feedback signal representing the output power, output voltage or output current.
FIG. 1 illustrates an example of a conventional flyback type switching power converter. The power converter includes a transformer 102, a diode 104, a switch 106, a pulse generator 110, and a buffer 108. The pulse generator 110 generates the pulses (output) 114 (or 202 in FIG. 2) that drive the switch 106. The buffer 108 buffers the logic level pulses 114 before they drive the switching device 106, and shifts the voltage level of the gate drive signal 107 to a high voltage suitable for driving the switch 106. The rectified AC power (DC) 112 is stored in the transformer 102 while the switch 106 is on and is transferred to the load (not shown) while the switch 106 is off. Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) are conventional techniques used for controlling the power converters by controlling the widths or frequencies of the pulses 114 driving the switch 106 to achieve output power regulation.
FIG. 2 illustrates ideal turn-on waveforms for the switch 106. The logic level 202 represents the logic waveform of the output signal 114 of the pulse generator 110, the signal 204 illustrates the voltage waveform of the gate drive signal 107, and the current signal 206 illustrates the current through the switch 106. In ideal situations, the buffer 108 would have zero propagation delay, and the switching device 106 would have zero turn-on and turn-off delay, such that the gate drive signal 204 (107 in FIG. 1) is synchronous with the output signal 202 (114 in FIG. 1), and the current signal 206 is synchronous with the gate drive signal 204 (107 in FIG. 1).
In real power converter circuits, however, the buffer 108 certainly has propagation delay tp, and the switching device 106 has significant turn-on delay ton—delay and turn-off delay toff—delay due to the parasitic capacitances and parasitic resistance in the switching device 106. For example, FIG. 3 illustrates a model of the MOSFET switch 106 that typically has parasitic resistance Rg and parasitic capacitances Cgd, Cgs, and Cds that cause the turn-on delay and the turn-off delay. The turn-off delay is generally longer than the turn-on delay, especially for BJT switches 106 due to the need for the minor electrons to be removed.
Thus, the real turn-on time ton of the switch 106 is given by: ton=tout−ton—delay+toff—delay where tout is the intended on-time of the switch 106 as indicated by the output pulse 114 generated by the pulse generator 110. Obviously, the turn-on delay and turn-off delay of the switch 106 are out of control, which affect output voltage regulation. The total error Δton of the on-time is given by:
      Δ    ⁢                  ⁢          t      on        =                              -                      t            on_delay                          +                  t          off_delay                            t        out              .  
FIG. 4 illustrates turn-on waveforms for the switch 106 in a real power converter circuit that has the propagation delays and the turn-on/turn-off delays. Due to the propagation delay tp, the gate drive signal 204, 107 rises 404 later than the rising edge 402 of the output signal 202, rises to its on-level slowly during the turn-on delay ton—delay, and drops to its off-level slowly during the turn-off delay toff—delay. It can be seen that, when the ideal width tout of the output pulse 114 is narrow, the total on-time error becomes relatively longer, which creates significant ripple at the output of the power converter. For example, when the intended on-time tout is 400 ns, but the total delays of turn-on and turn-off time are over 200 ns, the total error is over 50%. This will result in high ripple voltage at the output of the power converter, which is undesirable for any type of power converter.
Conventional solutions sought to reduce the turn-off delay of the switch 106 so that the output voltage (Vo) of the power converter can be better regulated. FIGS. 5 and 6 illustrate conventional solutions that minimize the turn-off delay time by shorting the parasitic resistance Rg (502 in FIGS. 5 and 6) of the MOSFET switch 106 using a diode 500 (FIG. 5) or BJT 600 (FIG. 6) across the parasitic resistance 402. The electrons of the switch 106 can be discharged faster through the diode 500 or BJT 600 during turn-off of the switch 106. However, the conventional solutions could not eliminate the propagation delay of the buffer 108 or the turn-on delay of the switch 106. Furthermore, because the electrical properties of the switch 106 vary from switch to switch, a fixed solution such as the diode 500 (FIG. 5) or BJT 600 (FIG. 6) is not very effective in eliminating the turn-off delay of the switch 106.
Therefore, there is a need for a technique for reducing or entirely eliminating the on-time delay of the switch caused by the propagation delay through the buffer and the turn-on/turn-off delays in switching power converters.